AS-SiliconMind/SiliconMind-V1-Qwen3-4B-T-2507
TEXT GENERATIONConcurrency Cost:1Model Size:4BQuant:BF16Ctx Length:32kPublished:Feb 11, 2026License:apache-2.0Architecture:Transformer Open Weights Warm

AS-SiliconMind/SiliconMind-V1-Qwen3-4B-T-2507 is a 4 billion parameter large language model from AS-SiliconMind, specialized for Verilog code generation, testing, and debugging. Fine-tuned from Qwen3-4B-Thinking-2507, it integrates reasoning-oriented training and self-correction mechanisms. This model excels at generating, testing, and debugging RTL designs, offering state-of-the-art functional correctness on major Verilog benchmarks.

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