What is chipcraftx-rtlgen-7b?

chipcraftx-rtlgen-7b is a 7.6 billion parameter language model developed by ChipCraftX, specifically designed for generating Register Transfer Level (RTL) Verilog code. It is fine-tuned from the Qwen2.5-Coder-7B-Instruct base model using QLoRA on a proprietary dataset of 76,811 Verilog training samples over three epochs. This model is the core local RTL generation engine for the ChipCraftX platform, which converts natural language specifications into synthesizable Verilog.

Key Capabilities & Performance

While the standalone chipcraftx-rtlgen-7b achieves a 36.5% functional pass rate on the VerilogEval-Human benchmark, its primary strength lies in its integration within the full ChipCraftX hybrid system. When combined with cloud models like Claude and automated EDA validation, the system achieves an impressive 98.7% functional pass rate on VerilogEval-Human (154/156 problems).

Intended Use Cases

• First-pass RTL/Verilog code generation from natural language specifications.
• Integration into automated Electronic Design Automation (EDA) pipelines with validation feedback loops.
• Educational use in digital design courses.
• Rapid prototyping of hardware modules.

Limitations

It's important to note that the standalone model's pass rate means approximately two out of three complex problems may require iteration or human review. It performs strongest on combinational logic and is weaker on Finite State Machines (FSMs) and sequential designs. Outputs target Verilog-2001 / Icarus Verilog compatibility, not full SystemVerilog, and should always be paired with EDA validation before production use.