vxkyyy/vlsi-moe-ffn-merged-formal
The vxkyyy/vlsi-moe-ffn-merged-formal model is a 33.8 billion parameter Qwen2-based language model, fine-tuned specifically for VLSI Formal Verification tasks. This model excels at generating SVA Assertions and Coverage Models, capabilities not present in its base model. It is optimized for specialized applications within the VLSI design flow, particularly for formal verification engineers.
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VLSI-MoE-FFN-Merged-Formal: VLSI Formal Verification Specialist
This model, developed by vxkyyy, is a 33.8 billion parameter Qwen2-based language model specifically fine-tuned for VLSI Formal Verification. It builds upon the vxkyyy/vlsi-moe-ffn-merged base model, enhancing its capabilities for highly specialized tasks within the VLSI design flow.
Key Capabilities
- RTL Generation: Inherits the ability to generate Register-Transfer Level (RTL) code.
- Testbench Generation: Capable of generating testbenches for design verification.
- SVA Assertions: New capability – excels at generating SystemVerilog Assertions (SVA), which are crucial for formal verification.
- Coverage Models: New capability – proficient in creating coverage models, essential for ensuring thorough verification.
Training Details
The model was fine-tuned using LoRA (r=128, α=256) over 10 epochs on a dataset comprising 307 SVA examples. This targeted training on formal verification data, utilizing AMD Instinct MI300X hardware, resulted in a final loss of 0.051, indicating strong specialization.
Good For
- Engineers and researchers working on VLSI Formal Verification.
- Automating the generation of SVA Assertions and Coverage Models.
- Specialized applications requiring an LLM with deep understanding of VLSI design and verification principles.