wyt2000/CodeV-SVA-14B
CodeV-SVA-14B is a 14 billion parameter large language model developed by wyt2000, specifically designed for hardware assertion generation. This model translates natural language verification properties into SystemVerilog Assertions (SVAs), leveraging a context length of 32768 tokens. It excels at converting human-readable specifications into executable SVA code, achieving high functional accuracy on both human-generated and machine-generated benchmarks. CodeV-SVA-14B is optimized for formal verification tasks in hardware design.
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CodeV-SVA-14B: Specialized LLM for SystemVerilog Assertion Generation
CodeV-SVA-14B is a 14 billion parameter model from the CodeV-SVA family, developed by wyt2000. Its core function is to translate natural language descriptions of hardware verification properties into SystemVerilog Assertions (SVAs). This specialization addresses a critical need in formal verification for Register Transfer Level (RTL) designs.
Key Capabilities and Performance
- Natural Language to SVA Translation: Directly converts human-readable verification requirements into precise SVA code.
- High Functional Accuracy: Achieves strong performance on dedicated benchmarks:
- NL2SVA-Human: Scores 75.8% Func.@1, 89.4% Func.@16, and 90.4% Func.@32.
- NL2SVA-Machine: Scores 84.0% Func.@1, 94.9% Func.@16, and 95.8% Func.@32.
- Competitive Benchmarking: Outperforms other models in its size class, such as Qwen3-14B and SVACoder-8B, on key NL2SVA metrics, demonstrating its specialized effectiveness.
- RTL-Grounded Synthesis: The model's training methodology involves RTL-grounded bidirectional data synthesis, enhancing its understanding of hardware design contexts.
Ideal Use Cases
CodeV-SVA-14B is particularly well-suited for:
- Automated SVA Generation: Accelerating the creation of SystemVerilog Assertions from design specifications.
- Formal Verification: Assisting verification engineers in developing comprehensive assertion suites for hardware designs.
- Reducing Manual Effort: Minimizing the manual translation of verification properties, thereby improving efficiency and reducing errors in the verification process.