The zhuyaoyu/CodeV-R1-Distill-Qwen-7B is a 7.6 billion parameter language model, based on the Qwen-2.5 series, specifically designed for generating hardware description languages (HDLs) like Verilog. This model is the distillation stage of the CodeV-R1 framework, which employs a novel RLVR algorithm for training Verilog generation LLMs. It excels at Verilog specification-to-RTL translation and code completion tasks, demonstrating superior performance on benchmarks like VerilogEval and RTLLM compared to other general and coding LLMs.
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CodeV-R1-Distill-Qwen-7B: Verilog Generation Model
This model, developed by zhuyaoyu as part of the CodeV-R1 project, is a 7.6 billion parameter language model derived from the Qwen-2.5 series. It is specifically engineered for generating Verilog code from natural language specifications, addressing challenges in electronic design automation (EDA) such as verification, data scarcity, and computational cost.
Key Capabilities & Features
- Verilog Generation: Optimized for creating hardware description languages (HDLs) like Verilog from natural language prompts.
- Distillation Stage: Represents the distillation phase of the CodeV-R1 framework, which utilizes a two-stage distill-then-RL training pipeline.
- Enhanced Verification: Leverages a rule-based testbench generator for robust equivalence checking against golden references.
- High-Quality Data Synthesis: Employs a round-trip data synthesis method to create a high-quality dataset of NL-code pairs, verified for consistency.
- Strong Performance: Achieves 65.2% on VerilogEval v2 for spec-to-RTL translation and 65.5% for completion, and 56.2% on RTLLM v1.1, outperforming many general and coding-specific LLMs in its size class.
- Reasoning Abilities: The acquisition of reasoning processes for Verilog problems also enhances its out-of-domain mathematical capabilities.
Usage Recommendations
It is recommended to use a specific system prompt during inference to guide the model's reasoning and output format, enclosing the reasoning process within <think> tags and the final Verilog code within <answer> tags, formatted with ````verilog` block.